Intel 8086: Revizyonlar arasındaki fark

Although partly shadowed by other design choices in this particular chip, the multiplexed bus limited performance slightly; transfers of 16-bit or 8-bit quantities were done in a four-clock memory access cycle (which was faster on 16-bit, although slower on 8-bit quantities, compared to typical contemporary "8-bit" CPUs). As instructions varied from 1 to 6 bytes, fetch and execution were made [[Concurrency (computer science)|concurrent]] (as it remains in today's x86 processors): The ''bus interface unit'' fed the instruction stream to the ''execution unit'' through a 6 byte prefetch queue (a form of loosely coupled [[pipelining]]), speeding up operations on [[processor register|registerregisters]]s and [[operand|immediateimmediates]]s, while memory operations unfortunately became slower (4 years later, this performance problem was fixed with the [[80186]] and [[80286]]). However, the full (instead of partial) [[16-bit]] architecture with a full width [[Arithmetic logic unit|ALU]] meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via carry), speeding up such instructions considerably. Combined with [[orthogonalization]]s of operations versus [[operand]]-types and [[addressing mode]]s, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below).

* The address and data buses were [[multiplexing|multiplexmultiplexed]]ed, forcing a slightly longer (33~50%) bus cycle than in typical contemporary 8-bit processors.

| colspan="17" | '''Ana Kayıtçılar ( register )''' <br />

| colspan="17" | '''İndeks kayıtçıları ''' <br />

| colspan="17" | '''Segment kayıtçıları''' <br />

| colspan="17" | '''Eğitim noktası''' <br />